Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
SRAM
Low (Active) Power Memory
The low power embedded SP SRAM utilizes a different architecture than typical memory compilers and is designed to be used in SoCs…
Overview
The low power embedded SP SRAM utilizes a different architecture than typical memory compilers and is designed to be used in SoCs that require low active power consumption. It uses foundry provided bit cell and complements industry’s commercially available embedded memory IP offerings to provide maximum flexibility for designers to meet power and performance goals.
Key features
- 35% lower active power
- 5% higher performance (at the same power level)
- Supports Retention and Power Down modes, with 65% lower leakage in Power Down mode
What’s Included?
- Design Kit & Tape Kit:
- Verilog Model and Synopsys Model
- LVS netlist (CDL format)
- GDSII layout file (GDSII format)
- LEF view and Antenna LEF view
- Antenna CLF model and Mbist model
- Memory Manual and Document
Specifications
Identity
Part Number
Low_(Active)_ Power_ Memory
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Provider
Learn more about SRAM IP core
Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures
Why SRAM PUF Technology Is the Bedrock of Dependable Security in Any Chip
Vincent van der Leest, Synopsys
AI-driven SRAM demand needs integrated repair and security
Increasing popularity of AI applications and DPU architecture has led to growing demand for higher SRAM densities, in turn placing challenges on SRAM yield and reliability.
A comparison of SRAM vs quantum-derived semiconductor PUFs
This article explores the relative performance of SRAM PUF and quantum-derived semiconductor PUF technologies for IoT security.
Basics of SRAM PUF and how to deploy it for IoT security
This article covers the basics of what an SRAM PUF (physical unclonable function) is and how it works, as well as the functionality it offers in internet of things (IoT) security as the trust anchor for any device.
Frequently asked questions about SRAM IP cores
What is Low (Active) Power Memory?
Low (Active) Power Memory is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.