Single Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 40 k
Foundry sponsored - Single Port Register File compiler - TSMC 55 nm uLPeFlash - Memory optimized for high density and low power -…
Overview
Key features
- REACH HIGHEST DENSITY
- Smart periphery design for significant gain in density
- EXTEND BATTERY LIFE
- Data retention mode at 1.2 V and 0.9 V to divide drastically the leakage compared to simple stand by mode
- Byte write capability
- MAKE INTEGRATION EASIER
- Data range flexibility allows easy addition of bits for redundancy or ECC purposes
- Address range flexibility allows easy addition of single rows for redundancy purposes
- ENABLE RIGHT ON FIRST PASS DESIGN
- Complete mismatch validation of the memory architecture taking in account local and global dispersion
- Extended validation for high coverage rate of the compiler
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Register File IP cores
What is Single Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 40 k?
Single Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 40 k is a Register File IP core from Dolphin Semiconductor listed on Semi IP Hub.
How should engineers evaluate this Register File?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Register File IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.