Vendor: Dolphin Semiconductor Category: SRAM

Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k

Single Port SRAM compiler - TSMC 110 nm HV_1.5V_5V_32V - Memory optimized for high density and low power - compiler range up to 3…

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Overview

Single Port SRAM compiler - TSMC 110 nm HV_1.5V_5V_32V - Memory optimized for high density and low power - compiler range up to 320 k

Key features

  • Migration of an existing architecture already available for other processes (90, 85, 55 nm)
  • Smart periphery design to reach the highest density
  • Memory designed with SVT MOS for periphery and SVT uHD PRBC from TSMC for memory core
  • Ultra Low dynamic power
  • Partitioned array
  • Variable write-mask capability
  • Flexible power routing: power ring or ring-less
  • Low leakage design
  • Stand by mode
  • Data retention mode at 1.5 V to divide leakage by 25% compared to simple stand by mode
  • Easy integration
  • Data range flexibility allows easy addition of bits for redundancy or ECC purposes
  • Address range flexibility allows easy addition of single rows for redundancy purposes
  • The Dolphin quality
  • Complete mismatch validation of the memory architecture taking into account local and global dispersion
  • Optional BIST for industrial fabrication test of instances
  • Compliance with TSMC IP 9000 qualification process

Specifications

Identity

Part Number
SpRAM-RHEA-HD-RR_TSMC_110nm_HV32_Generator
Vendor
Dolphin Semiconductor
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Dolphin Semiconductor

Learn more about SRAM IP core

New Power Management IP Solution Can Dramatically Increase SoC Energy Efficiency

This Position Paper describes a family of Power Management IP solutions integrated by Dolphin Integration’s customers into their SoC to drastically improve Energy Efficiency (EE). SoC performance metric is changing, moving from pure performance metric (GHz or MIPS) to performance efficiency and minimum power consumption. This new metric, already crucial for IoT or mobile devices, is becoming key in various applications, like automotive, embedded or space.

Improving Battery-Powered Device Operation Time Thanks To Power Efficient Sleep Mode

Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC (System on Chip). For such applications, the design of the “Always-On power domain" (a.k.a AON power domain) is pivotal.

Cache Evaluation Software: A Dynamically Configurable Cache Simulator

The memory hierarchy (including caches and main memory) can consume as much as 50% of an embedded system power. This power is very application dependent, and tuning caches for a given application is a good way to reduce power consumption. However application programs are complex and include many subroutines, each of them having their own optimal cache configuration. We developed a low power dynamically reconfigurable cache controller and its simulator called Cache Evaluation Software.

Frequently asked questions about SRAM IP cores

What is Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k?

Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k is a SRAM IP core from Dolphin Semiconductor listed on Semi IP Hub.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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