UMC 28nm HPM/LVT Logic Process 9-track ECO_M1 core cell library (C35)
UMC 28nm HPM/LVT Logic Process 9-track ECO_M1 core cell library (C35)
- UMC
- 28nm
- HPM
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
UMC 28nm HPM/LVT Logic Process 9-track ECO_M1 core cell library (C35)
UMC 28nm HPM/LVT Logic Process 9-track ECO_M1 core cell library (C35)
UMC 28nm HPM/LVT Logic Process 9-track ECO_M1 core cell library (C31)
UMC 28nm HPM/LVT Logic Process 9-track ECO_M1 core cell library (C31)
UMC 28nm HPM/HVT Logic Process 9-track Standard cell ECO_M1 CORE library (C38)
UMC 28nm HPM/HVT Logic Process 9-track Standard cell ECO_M1 CORE library (C38)
UMC 28nm HPM/HVT Logic Process 9-track Standard ECO_M1 cell library (C35)
UMC 28nm HPM/HVT Logic Process 9-track Standard ECO_M1 cell library (C35)
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias.
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90).
UMC 55nm eFlash/RVT LowK Logic Process 8-track ECO_M1 cell Library
UMC 55nm eFlash/RVT LowK Logic Process 8-track ECO_M1 cell Library
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library
UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library
UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library enhanced for routing (C35)
UMC 55nm eFlash/RVT Logic Process 7-track ECO_M1 cell library
UMC 55nm eFlash/RVT Logic Process 7-track ECO_M1 cell library
UMC 55nm eFlash/LVT Logic Process 7-track ECO_M1 Generic cell library
UMC 55nm eFlash/LVT Logic Process 7-track ECO_M1 Generic cell library
UMC 55nm eFlash/HVT Logic Process 7-track ECO_M1 cell library
UMC 55nm eFlash/HVT Logic Process 7-track ECO_M1 cell library