VeriSilicon Introduces GLTiny™ 3D GPU Programming Model for Ultra-Low-Power, Memory-Efficient Wearable Devices
Optimized GLTiny Model Brings Rich 3D Graphics to Resource-Constrained Wearable Devices Powered by OpenGL ES GPUs
VeriSilicon SMIC 0.11um Ultra Low-Leakage Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Cor…
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 130nm | G | Pre-Silicon |
SMIC 0.13um 90% shrunk HVT Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic Pre-Silicon.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.