Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: SRAM

SMIC 0.18umLL 90% shrunk Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler

VeriSilicon SMIC 0.16um Low Leakage Process Synchronous Memory Compiler optimized for Semiconductor Manufacturing International C…

SMIC 180nm G Pre-Silicon View all specifications

Overview

VeriSilicon SMIC 0.16um Low Leakage Process Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.16?m Logic 1P6M Salicide 1.8/3.3V Low Leakage process can flexibly generate memory blocks via a friendly GUI or shell commands.
The compiler supports a comprehensive range of word and bit lengths. While satisfying speed and power requirements, it is optimized for area efficiency.
VeriSilicon SMIC 0.16um Low Leakage Process Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5, or 6 as the top metal. Dummy bit cells are synthesized with the intention to enhance reliability

Key features

  • Low Power
  • Low Leakage
  • High Density
  • High Speed
  • Size Sensitive Self-Time Delay for Fast Access
  • Automatic Power Down
  • Tri-State Output(SRAM only)
  • Write Mask Function(SRAM & Register File)

Silicon Options

Foundry Node Process Maturity
SMIC 180nm G Pre-Silicon

Specifications

Identity

Part Number
SMIC16LL MC
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about SRAM IP core

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

The authors propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO2/ZrO2/HfO2 (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology.

Frequently asked questions about SRAM IP cores

What is SMIC 0.18umLL 90% shrunk Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler?

SMIC 0.18umLL 90% shrunk Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic Pre-Silicon.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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