Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for …
- UCIe
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for …
Non-Coherent Network-on-Chip (NOC)
Performance (bandwidth and latency) optimized non-coherent NOC solution that significantly reduces silicon wire utilization, resu…
MSquare's HBM3 IP (the 3rd generation of High-Bandwidth Memory) is specifically tailored for applications that require high memor…
SEC 5nm LVH 6T Multi-Bits Latch
SEC 5nm LVH 6 track High Density Multi-Bits Latch
TSMC 12nm FFC 6track Delay Cells
TSMC 12nm FFC 6 track High Density Delay Cells
SMIC 0.13um 1.2V<->3.3V level shifter,1.2v/3.3v operating voltage
SMIC 0.13um 1.2V3.3V Level Shfiter Library
SMIC 0.13um Power Management Kit,1.2v operating voltage
SMIC 0.13um Power Management Kit Library
SMIC 0.13um 6 track High Density Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.13um 6T HVT High-Density Standard Cell Library
All self-developed domestic IPs
VeriSyno offers network IP solutions tailored for the high-end server market.
This IP is composed of a single to sextuple channel 10-bit, 300MHz DAC designed for 40nm CMOS technology supplied at 3.3V.
The HDMI Tx PHY is the physical layer of a single-link HDMI transmitter interface.
The HDMI Rx PHY is the physical layer of an HDMI receiver.
The DDR4 multiPHY is a mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a S…
The DDR multiPHYs are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 S…
The DDR3/2 PHY is a mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design ta…
The XAUI PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into XAUI …
The SATA 6G PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SA…
The PCIe2 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI …
The PCIe1 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into comp…
The MIPI D-PHY RX 2/4 Lanes macro implements the physical layer of universal lanes for the MIPI D-PHY interface, stacked in a two…