Overview
This IP is composed of a single to sextuple channel 10-bit, 300MHz DAC designed for 40nm CMOS technology supplied at 3.3V. Each independent DAC uses a segmented current steering architecture, combined with an improved two-dimensional centroid switching scheme, to achieve simultaneously high update rates, at least 10-bit of intrinsic static accuracy, and very good dynamic characteristics. The circuit is a current output DAC designed to be loaded by double terminated 75 Ohm Lines. The DAC full-scale current is set with the internal bandgap reference voltage, an external resistor and a digital 6 bit word. Sense comparators are included to allow power savings when video cables are disconnected. This Video DAC is suitable for RGB video and HDTV or standard Video (Component, S-Video, Composite) applications.
Learn more about DAC IP core
Brett Cline, Codasip
Brett Cline, Codasip
Brett Cline, Codasip
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
Lauro Rizzatti, Verification Consultant