Low Power D2D Interface in TSMC 16nm FFC/FFC+
A 600MBps Low Power Die-to-Die Interface in TSMC 16nm FFC/FFC+.
- TSMC
- 16nm
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Low Power D2D Interface in TSMC 16nm FFC/FFC+
A 600MBps Low Power Die-to-Die Interface in TSMC 16nm FFC/FFC+.
RF ESD library in TSMC 55nm LP
RF ESD cells in TSMC 55nm LP targetting low-capacitance ESD protection.
6.5V ESD Clamp in 180nm Technology
Standalone 6.5V ESD Power Clamp in 180nm technology for use in wirebond or flipchip.
5V ESD Clamp in GlobalFoundries 180nm LPe
A GlobalFoundries 180nm LPe Specialized 5V ESD Clamp.
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
The Bitec Camera Front End IP allows developers to interface CMOS and CCD cameras to an Altera FPGA.
The Bitec HDMI 2.1b IP Core enables HDMI interconnectivity in FPGA or ASIC devices.
Column-parallel high resolution, high speed ADC
Massar is a column-parallel high resolution, high speed ADC tailored to low power consumption and large frame imaging sensors.
Advanced On-Die DroopTelemetry
The Aeonic Insight Droop Detector is used as part of the Movellus Integrated Droop Response System comprised of the Aeonic Insigh…
LPDDR Secure Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR Secure Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
The LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC st…
Low Power BTDM5.3 Connectivity Transceiver
IP
optimized for generative AI applications running Transformer based NN models that enables efficient and simple system designs.
4x improvement to vector computation with 4x sustained bandwidth of prior generations
Building on the popular SiFive Intelligence™ X280 products’ success in AI/ML applications across mobile, infrastructure and autom…
The highest performance RISC-V core is ideal for consumer applications or used in conjunction with a vector processor in the data…
tRoot V023 FS Hardware Secure Module, ASIL-B compliant (w/ ARC EM22FS)
The ASIL B certified Synopsys tRoot™ Hardware Secure Module (HSM) for Automotive augments its comprehensive root of trust securit…
Optimized for machine learning, video and imaging workloads
HMAC-SHA256 cryptographic accelerator
The HMAC-SHA256 cryptographic accelerator function is used to securely generate and verify message authentication codes.
PCIe 5.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
The configurable and scalable the Controller IP for PCI Express® (PCIe®) supports all required features of the PCI Express 5.0, 4…