Low-Power Design for Multi-Display and High Quality Image Processing
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Low-Power Design for Multi-Display and High Quality Image Processing
Single Port High Speed SRAM Memory Compiler on N22ULL
Single port SRAM compiler with low power retention mode.
Dual Port (1 read only port, 1 write only port) Register File Compiler on N22ULL
Two port register file (1R1W) with low power retention mode Bit Cell Power Supply (V) 8T 0.9
Single Port Register File Compiler on N22ULL
Single port register file compiler with low power retention mode Bit Cell Power Supply (V) 6T 0.9
Single Port Low Voltage SRAM Memory Compiler on N22ULL - Low Power Retention and Column Repair
Single Port SRAM Compiler with Low Power Retention Mode and Ultra Low Leakage Bit Cell Power Supply (V) 6T 0.9
Single Port Low Voltage SRAM Memory Compiler on N22ULL
Single port SRAM compiler with low power retention mode.
DSI-2 TX/RX IP supports both transmit and receive functions in line with the DSI-2 v1.1 and D-PHY v2.0 standards.
CSI-2 RX IP supports both C-PHY v1.2 and D-PHY v2.0 interfaces, enabling flexible integration across a wide range of image sensor…
The DSC Decoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
The DSC Encoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
112G VSR PHY, TSMC N5 x8, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…
UCIe Controller baseline for Streaming Protocols
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
512x1 Bits OTP (One-Time Programmable) IP, MXIC 0.18um 1.8V/5V CMOS 18B Process
The ATO00512X1MX180LB52ND is organized as a 512-bit by 1 one-time programmable (OTP).
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
112G PHY, TSMC N5 x2, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…
The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package.
LPDDR5X/5/4X PHY - SS SF5A for Automotive, ASIL B Random, AEC-Q100 Grade 2
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…
The NB-IoT NTN System Test Bench (STB) is a cost-effective, flexible testing environment for NB-IoT NTN eNodeB product developers.
Two-Digit Nanosecond PCIe 7.0-CXL 4.0 Link Controller IP
The PCIe PHY IP supports PCIe Gen 4.0, 5.0, and 6.0, and is validated through interoperability testing in collaboration with glob…