Low power 32-bit processor with secure execution capability
E803 utilizes a 3-stage sequential pipeline to achieve an optimized balance between performance and cost.
- CPU
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Low power 32-bit processor with secure execution capability
E803 utilizes a 3-stage sequential pipeline to achieve an optimized balance between performance and cost.
Ultra-low power 32-bit processor with secure execution capability
E802 utilizes a 2-stage minimalistic pipeline and optimizes average and peak power consumption.
Ultra-low-cost 32-bit processor
E801 is has the lowest cost and lowest power consumption among T-Head processors.
High-performance 32-bit multi-core processor with AI acceleration engine
C860 utilizes a 12-stage superscalar pipeline, with a standard memory management unit, and can run Linux and other operating syst…
Poly-IP-53 (EIP-53) is IP for accelerating the Poly1305 hash-based message authentication algorithm (RFC7539), supporting the NIS…
The IPrium-ATSC-8VSB-Modulator IP Core implements the USA DTV standard ATSC A/53 Part 2.
TC5300 is an efficient Polar encoder/decoder Core solution compliant with 3GPP NR (5G) specifications.
TC5200 is an efficient LDPC encoder/decoder Core solution fully compliant with 3GPP NR (5G) specifications.
AXI4-Stream to/from AXI Memory Map - AXI Memory Map Conversion to AXI4-Stream, 16 Channels
The DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the a…
AXI4-Stream to/from AXI Memory Map - AXI4-Stream Conversion to AXI Memory Map, 16 Channels
The DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to …
The SerDes PHY IP meets the requirements of broad range of market segments including network communication, PC interconnect, data…
GP ULP Temperature Sensor - Built-in Sigma-Delta modulator – Low Quiescent Current - Silterra 0.18um
This macro-cell is an ultra-low-power, general purpose temperature sensor core.
True-ULP 32.768kHz RTC Oscillator - Current Consumption<120nA - Silterra 0.18µm
This macro-cell is a true ultra-low-power, general purpose 32.768kHz internal oscillator core consuming 120nA when fully function…
6MHz ±1% PVT 1.8V Low Power Oscillator in Silterra 0.18um
This macro-cell is a low-power, precision, general purpose 1.8V 6MHz ±1% PVT internal oscillator core aimed for clock generation.
6MHz 3.3V Low Power Oscillator - ±1% after trimming. Re-targetable to 1-30MHz - Silterra 0.18µm
This macro-cell is a low-power, precision, general purpose 3.3V 6MHz ±1% PVT internal oscillator core aimed for clock generation.
ULP 32.768kHz oscillator in Silterra 0.18 um
This macro-cell is an ultra-low power, general purpose 32.768kHz internal oscillator core aimed for RTC (real time clock) applica…
USB 3.1 is the most recent version of the USB (Universal Serial Bus) standard for connecting electronic devices in host and devic…
Serial Front Panel Data Port Gen3
Serial Front Panel Data Port Gen3 is a next-generation, high bandwidth serial communications protocol defined by the ANSI/VITA 17…
1G IP/UDP full HW Stack Transmitter / Receiver
To efficient transfer large amount of data and off-load the system processor, BitSim has launched its IP, Bit-UDP Ethernet.
OT3910bj is a set of cells designed for implementing the transmitter, receiver and associated bias function for LVDS point to poi…