SerDes IP Listing

This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.

• Multi-Protocol PHY

The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.

• TSMC
• 3nm
• N3P

The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.

• TSMC
• 3nm
• N3E

The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.

• TSMC
• 2nm
• N2P

Designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G The 32…

• PHY
• GlobalFoundries
• 22nm
• In Production

Extoll’s SerDes architecture is based on digital design elements and methodologies.

• GlobalFoundries
• 12nm
• LP

Extoll’s SerDes architecture is based on digital design elements and methodologies.

• GlobalFoundries
• 12nm
• LP

The PCIe 2.0 transceiver IP supports all PCIe 2.0 Base applications.

• SMIC
• 14nm
• SF+
• In Production

Compliance with the PCIe 3.0 Base Specification is standardized by the PCIe 3.0 PHY IP with PIPE 4.3 interface standard.

• SMIC
• 40nm
• LP
• In Production

The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP.

• TSMC
• 40nm
• ULP
• In Production

The whole spectrum of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP.

• TSMC
• 16nm
• FFC
• In Production

A wide variety of PCIe 2.0 Base applications are available with PCIe 2.0 transceiver IP.

• TSMC
• 12nm
• FFC
• In Production

A comprehensive selection of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP.

• TSMC
• 7nm
• N7+
• In Production

The PCIe 3.0 PHY IP is designed to support increased applications with its low-power, multi-lane, high-performance design.

• TSMC
• 22nm
• ULP
• In Production

High-bandwidth applications can avail advantage of PCIe 3.0 PHY IP's high performance, multi-lane scalability, and low-power layo…

• TSMC
• 16nm
• FFC
• In Production

To support high-bandwidth applications, PCIe 3.0 PHY IP provides a low-power, multi-lane, high-performance design.

• TSMC
• 12nm
• FFC
• In Production

For the high-bandwidth applications, PCIe 3.0 PHY IP offers high-performance, multi-lane capabilities, and low-power design.

• TSMC
• 7nm
• N7+
• In Production

For high-bandwidth applications, the PCIe 4.0 PHY IP delivers high-performance, multi-lane capabilities and a low-power design.

• TSMC
• 16nm
• FFC
• In Production

The high-bandwidth applications benefit from the low power, multi-lane, and high-performance PCIe 4.0 PHY IP's design.

• TSMC
• 7nm
• N7+
• In Production

For high-bandwidth applications, the PCIe 5.0 PHY IP offers excellent performance, multi-lane capabilities, and low power design.

• TSMC
• 16nm
• FFC
• In Production