CAST IP Listing

The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, wh…

• DMA

The ECC-SRAM core adds protection against SRAM data corruption.

• Channel Coding

This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 s…

• Image Conversion

The SafeSPI-CTRL implements a versatile and reliable Serial Peripheral Interface (SPI) controller compliant with the SafeSPI spec…

• SPI / QSPI XSPI

LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithm…

• Data Compression

GEON-SBoot is an area-efficient, processor-agnostic hardware engine that protects SoC designs from booting with malicious or othe…

• Root Of Trust

The I3C-SC core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Secondary Controller core compliant with the…

• I2C / I3C

The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C b…

• I2C / I3C

The PNG-E core implements a lossless image compression engine compliant with the Portable Network Graphics (PNG) file format spec…

• Image Conversion

The SHA-384/512 is a high-throughput, and compact hardware implementation of the SHA-384 and the SHA-512 cryptographic hash funct…

• SHA2 (SHA-512)

The I2S-TDM IP core is a configurable, full-duplex, multichannel serial audio transceiver.

• I2S

The PWM IP core implements a compact and flexible Pulse Width Modulator.

• Power Management Controller

The PNG-D core implements a lossless image decompression engine compliant with the Portable Network Graphics (PNG) file format sp…

• Image Conversion

The QOID Core is a decoder that implements a efficient, low-power, lossless image decompression engine compliant with the Quite O…

• Image Conversion

The QOIE Core is an encoder that implements a efficient, low-power, lossless image compression engine compliant with the Quite OK…

• Image Conversion

The EMSA5-FS is a processor core designed for functional safety.

• RISC-V

The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, wh…

• Bus Fabric

The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI…

• Protocol Bridge

The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slav…

• Bus Fabric

The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves.

• Bus Fabric