Overview
This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, hardware JPEG encoder with very low processing latency. Probably the smallest JPEG encoder IP core in the market, the JPEG-E-T occupies about 40,000 equivalent NAND2 gates.
The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames.
SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.
The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.
Learn more about Image Conversion IP core
In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting. But the meaning of “low latency” can vary, and the methods for achieving low latency aren’t always obvious. Here we’ll define and explain the basics of video latency, and discuss how one of the biggest impacts in reducing latency comes from choosing the right video encoding.
In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting.
Computer vision has made tremendous advances in the last several years due to the proliferation of AI technology. The intersection of big data and massive parallel computing changed the way in which machines are programmed to understand unstructured 2D and 3D data, such as video feeds from cameras.
Traditional IC design options that embedded system designers have had to choose from include fixed hardware devices such as standalone microprocessors, microcontrollers and ASSPs or configurable hardware devices such as FPGAs and cell-based ASICs. In this paper we present a new design option called Nextreme Structured ASICs which provide embedded system designers with a compelling alternative to custom embedded system design.
By Hantro
Configurable Processors for Video Processing SOCs
