Tiny Baseline JPEG Encoder

This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, hardware JPEG encoder with very low processing latency. Probably the smallest JPEG encoder IP core in the market, the JPEG-E-T occupies about 40,000 equivalent NAND2 gates. 

The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. 

SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface. 

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.
 

• Extremely small JPEG encoder 
• Standards Support
  • ISO/IEC 10918-1 Standard Baseline Encoder (Sequential DCT modes)
  • Encodes single-frame JPEG images and Motion JPEG payloads
  • 8-bit color samples
  • Up to four color components; any image size up to 64k x 64k 
  • Handles all scan configurations and all JPEG formats 
  • APP, COM, and restart markers
  • Programmable Quantization table, for image quality or bit rate control
• Interfaces
  • AXI Streaming input and output data interfaces
  • APB Control/Status interface
  • Optional AHB wrapper with DMA capabilities
• Performance and Size
  • One encoded sample per clock cycle
  • Small silicon footprint (40,000 Gates)
• Ease of Integration
  • Automatic program-once/encode-many operation
  • Simple, dedicated timestamps interface 
  • Included bit-accurate software model generates test vectors, expected results, and core programming values
  • Optional Raster-to-Block Conversion with AXI or standard memory interface to the lines buffer
• Format
  • Available as a targeted FPGA netlist