Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 55SP
The maximum capacity of the Display Port 1.4 Rx IP Channel is supported.
- Single-Protocol PHY
- In Production
- Immediate
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 55SP
The maximum capacity of the Display Port 1.4 Rx IP Channel is supported.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 55SP
The DisplayPort transmitter PHY version 1.4 can transmit data at rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
V-by-One Rx IP, Silicon Proven in 40G
Using internal equipment connections, the V-by-One HS technology seeks to send video signals at a high data rate.
V-by-One Tx IP, Silicon Proven in 40G
The V-by-One HS technology aims to transmit video signals at a high data rate using an internal connection between devices.
V-by-One/LVDS Tx Combo PHY, Silicon Proven in 28HPC+
V-by-One/ LVDS Tx Combo PHY IP Core aims at achieving high-speed data transmission for video signals through internal equipment c…
Latch-Up Protection Module with 2-inputs 3-Outputs - 7nm
The ODT-LUP-2I3O-7 is a latch-up detection solution that can support integration into FinFET process nodes such as N7.
Ultra low-power crystal-based 32 kHz oscillator
High accuracy 32 kHz Crystal oscillator with low-power consumption and low shutdown current to be used in the AON domain to imple…
Power Management IC - I3C Basic Interface IP
Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application.
OPEN Alliance TC6 10BASE-T1S MACPHY Interface
The CT25209 Digital IP core implements the MACPHY SPI protocol defined by the “OPEN Alliance TC6 Serial 10BASE-T1x MACPHY Interfa…
The CT25208 Digital IP core is a standard Clause 4 CSMA/CD MAC exposing a proprietary, FIFO-like MAC Client interface (TX/RX).
IEEE 802.3cg® 10BASE-T1S Analog Front-End
The CT25203 implements the analog front end of an IEEE 802.3cg® 10BASE-T1S physical layer.
RISC-V CPU IP With ISO 26262 Automotive Functional Safety Compliant
AndesCore™ N25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications.
JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
The JESD 204B controller IP is optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, F…
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SMIC 28SF
The GPHY is a integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption.
The TCPIP-1G/10G core implements a TCP/IP Hardware Protocol Stack.
Successive Approximation Register (SAR), interleaved 8-fold • Operating temperature 50 to 350 Kelvin • Radiation tolerant (TID > …
24-bit Sigma Delta Stereo Audio Ulter low area silicon provenin 28nm DAC
low-cost stereo digital to analog converter for audio applications.
18-bit Sigma Delta Stereo Audio 28nm silicon proven in TSMC 28HPC ADC
This is a low-cost stereo analog to digital converter for digital audio applications.
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 40LP
Compliance with the PCIe 3.0 Base Specification is standardized by the PCIe 3.0 PHY IP with PIPE 4.3 interface standard.
HomePlugAV is a new standard designed to provide the high data rates and guaranteed Quality of Service (QoS) required by today’s …