Power Management IC - I3C Basic Interface IP
Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application.
- I2C / I3C
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Power Management IC - I3C Basic Interface IP
Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application.
OPEN Alliance TC6 10BASE-T1S MACPHY Interface
The CT25209 Digital IP core implements the MACPHY SPI protocol defined by the “OPEN Alliance TC6 Serial 10BASE-T1x MACPHY Interfa…
The CT25208 Digital IP core is a standard Clause 4 CSMA/CD MAC exposing a proprietary, FIFO-like MAC Client interface (TX/RX).
IEEE 802.3cg® 10BASE-T1S Analog Front-End
The CT25203 implements the analog front end of an IEEE 802.3cg® 10BASE-T1S physical layer.
RISC-V CPU IP With ISO 26262 Automotive Functional Safety Compliant
AndesCore™ N25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications.
JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
The JESD 204B controller IP is optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, F…
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SMIC 28SF
The GPHY is a integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption.
The TCPIP-1G/10G core implements a TCP/IP Hardware Protocol Stack.
Successive Approximation Register (SAR), interleaved 8-fold • Operating temperature 50 to 350 Kelvin • Radiation tolerant (TID > …
24-bit Sigma Delta Stereo Audio Ulter low area silicon provenin 28nm DAC
low-cost stereo digital to analog converter for audio applications.
18-bit Sigma Delta Stereo Audio 28nm silicon proven in TSMC 28HPC ADC
This is a low-cost stereo analog to digital converter for digital audio applications.
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 40LP
Compliance with the PCIe 3.0 Base Specification is standardized by the PCIe 3.0 PHY IP with PIPE 4.3 interface standard.
HomePlugAV is a new standard designed to provide the high data rates and guaranteed Quality of Service (QoS) required by today’s …
IEEE 802.11n/ac/ax Encoder and Decoder
The IPrium-LDPC-802.11-WIFI-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algorithm…
Modular, high performance 5G NR Layer 1 (PHY) solutions for Non-Terrestrial Network applications
AccelerComm’s physical layer solution is optimised for 5G satellite hybrid networks and related applications.
32-bit RISC-V processor specifically designed for the Automotive and Functional Safety markets
The SiFive Automotive™ E6-A series is designed for a variety of real-time, 32-bit applications, from system control to hardware s…
Embedded OTP (One-Time Programmable) IP, 8Kx8 bits for 5V Analog_BCD_G1S
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 8Kx8 bits for 3.3V Green
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 8Kx8 bits for 1.8V/3.3V RFCMOS
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 8Kx8 bits for 1.8V/3.3V Logic
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…