PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- PCIe Gen3
- Samsung
- 8nm
- 8LPP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3 SERDES PHY on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen3 SERDES PHY on Samsung 7LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3 SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
ONFI 3.0 Compatible I/O Buffer on TSMC CLN28HPL
The ONFI 3.0 compatible I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demande…
Multi Rail LDO for SERDES on TSMC CLN3P-CLN3X
The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.
Multi Rail LDO for SERDES on TSMC CLN3E
The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.
Multi Rail LDO for SERDES on TSMC CLN2P
The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.
Low Power Wide Range PLL on GLOBALFOUNDRIES 65LPE
The Low Power Wide Range PLL addresses markets and applications that demand very low power and optimized for area efficiencies.
Low Power Wide Range PLL on GLOBALFOUNDRIES 40LP
The Low Power Wide Range PLL addresses markets and applications that demand very low power and optimized for area efficiencies.
Low Power Wide Range PLL on GLOBALFOUNDRIES 28SLP
The Low Power Wide Range PLL addresses markets and applications that demand very low power and optimized for area efficiencies.
Low Power PLL on TSMC CLN90G-GT-LP
The low-power wide range PLL addresses markets and applications that demand very low power and optimized for area efficiencies.
The Low Power Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock…
Low Power PLL on TSMC CLN40LP-ULP
The Low Power Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock…
The Low Power Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock…
Low Power PCIe3/SATA3 Gen3 PHY on TSMC CLN28HPC+
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Low Power PCIe Gen3 PHY on TSMC CLN16FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Low Power PCIe Gen3 PHY on TSMC CLN12FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).