Vendor: Analog Bits Inc. Category: PLL

Low Power Wide Range PLL on GLOBALFOUNDRIES 28SLP

The Low Power Wide Range PLL addresses markets and applications that demand very low power and optimized for area efficiencies.

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GlobalFoundries 28nm SLP View all specifications

Overview

The Low Power Wide Range PLL addresses markets and applications that demand very low power and optimized for area efficiencies. In addition, consumer devices have restrictions on supply voltage due to battery restrictions or board restrictions. The PLLs are designed for standard digitallogic processes and implement robust design techniques to work in noisy SoC environments. The PLLs can address a large portfolio of applications, ranging from non-integer clock multiplication to programmable clock synthesis for multi-clock generation.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and EGPFET/EGNFET 1.8V medium-oxide IO devices. The PLL resides inside the IO ring that includes two analog power supply pads, occupying no core area. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power. The PLL macro fits into any standard IO pad pitch and is available for both staggered and in-line IOs.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 5 200 MHz Post-Divide Reference Frequency FPFD 5 200 MHz VCO Frequency FVCO 1500 3000 MHz Output Frequency FOUT 25 3000 MHz Output Duty Cycle for FOUT <1500MHz tDO 45 55 % Output Duty Cycle for undivided outputs tDO 40 60 % Lock Time tLOCK 60 µs Total area of macro (excluding bond pad area) A 0.02 sq. mm May vary depending on size of IO slots Chip core area requirement CA 0 sq. mm Total Power IDD 3 mA Operational Voltage (Digital) VDIG 0.9 1.0 1.1 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V (options available for other IO voltages) Operational Temperature TOP -40 25 125 C Table 1: PLL Operational Range

Key features

  • Electrically Programmable PLL for multiple applications
  • Wide Ranges of Input and Output Frequency for diverse clocking needs
  • Implemented with Analog Bits’ proprietary architecture
  • Fully integrated inside industry standard or other customized IO ring
  • Occupies zero core area
  • Low power consumption
  • Spread Spectrum tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption
  • Excellent jitter performance with optimized noise rejection

Block Diagram

Low Power Wide Range PLL on GLOBALFOUNDRIES 28SLP block diagram

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 28nm SLP —

Specifications

Identity

Part Number
Low Power Wide Range PLL on GLOBALFOUNDRIES 28SLP
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Contact Analog Bits Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Low Power Wide Range PLL on GLOBALFOUNDRIES 28SLP?

Low Power Wide Range PLL on GLOBALFOUNDRIES 28SLP is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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