Vendor: V-Trans Microelectronics Category: DAC

Triple DAC 10-Bits, voltage output - 10Mhz, 3.3V/1.3V full-scale

This IP is a triple channel 10-bits 10 MS/s general purpose voltage output DAC, optimized for analog LCD controller application a…

Overview

This IP is a triple channel 10-bits 10 MS/s general purpose voltage output DAC, optimized for analog LCD controller application and designed for industry standard 0.18um 1P6M CMOS technology supplied at 3.3V.

Each independent DAC uses an internal segmented current steering architecture, with at least 10-bit of intrinsic static accuracy, combined with an high slewrate (120V/uS), and high output current (up to 36mA), rail to rail voltage output driver.

A 1V full scale option allow the DAC to also deliver standard video signals on a 37.5Ω termination.

Key features

  • Programmable full scale : 3V or 1V.
  • 10 Bits resolution.
  • 10MS/s update rate.
  • Adjustable max output current 24, 30 or 36mA.
  • 3.3V ±10% supply voltage, -40/+125°C temperature.
  • 1P6M layout structure based on 0.18um 1P6M 3.3V/1.8V generic logic process.
  • Individual DAC channel Power down.
  • Do not require extra external bias circuit.
  • Cell area: [contact us]

Benefits

  • Analog LCD source driver

What’s Included?

  • Design Kit includes:
    • LEF view and abstract gdsII
    • Verilog HDL behavioral model
    • Liberty (.lib) timing constraints for typical, worse and best corner case
    • Full Datasheet /Application Note with integration guidelines document
    • Silicon characterization report when available
  • Tapeout kit includes the design kit plus plysical view:
    • gdsII
    • LVS netlist and report
    • DRC/ERC/ESD/ANT report

Specifications

Identity

Part Number
VT18DA10B3V
Vendor
V-Trans Microelectronics
Type
Silicon IP

Analog

Resolution bits
10 Bit

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is Triple DAC 10-Bits, voltage output - 10Mhz, 3.3V/1.3V full-scale?

Triple DAC 10-Bits, voltage output - 10Mhz, 3.3V/1.3V full-scale is a DAC IP core from V-Trans Microelectronics listed on Semi IP Hub.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP