Vendor: Archband Labs Inc. Category: PLL

40-450MHz Programmable Clock Generator PLL, SMIC0.13um

The AR530S13 is a low power programmable phase locked loop (PLL) featured with wide output frequency range from 50MHz to 450MHz.

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SMIC 130nm G In Production View all specifications

Overview

The AR530S13 is a low power programmable phase locked loop (PLL) featured with wide output frequency range from 50MHz to 450MHz. The PLL synchronizes two output clocks with an external reference clock through the locked loop mechanism. The output duty cycle is adjusted to 50%, independent to the reference clock. The PLL contains built-in 6-bit reference divider, 12-bit feedback divider and two 4-bit output divider that may be used in combination to provide flexible output frequencies.

Key features

  • Low jitter clock generator
  • Two programmable outputs
  • On-chip regulator
  • Small size suitable for multiple usage in single chip

What’s Included?

  • Full Datasheet
  • Application Note
  • Integration Guidance
  • Behavior Model
  • GDSII Abstract (.LEF Format)
  • Timing Library (.LIB Format)
  • LVS Netlist (SPICE Compatible)
  • Physical Design Database (GDSII Format)
  • Silicon Validation Report
  • AE Support

Silicon Options

Foundry Node Process Maturity
SMIC 130nm G In Production

Specifications

Identity

Part Number
AR530S13
Vendor
Archband Labs Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Archband Labs Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 40-450MHz Programmable Clock Generator PLL, SMIC0.13um?

40-450MHz Programmable Clock Generator PLL, SMIC0.13um is a PLL IP core from Archband Labs Inc. listed on Semi IP Hub. It is listed with support for smic In Production.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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