This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
- Single-Protocol PHY
- please contact us
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
This receiver converts 10 LVDS, (low voltage differential signaling) data streams, into 30bits dual pixel CMOS data plus 10 contr…
V-Trans ‘s FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow …
FPD-link, 30-Bit Color LVDS Receiver, 20-112Mhz
V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow …
The TXT_OVERLAY IP Core is a versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RG…
CAN Controller Core with 32/32 Message Objects
CANmodule-IIIx is a full functional CAN controller module that supports the concept of mailboxes.
BitBLT Graphics Hardware Accelerator (AXI4 Bus)
The DB9100AXI4 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from comma…
BitBLT Graphics Hardware Accelerator (AHB Bus)
The DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from comman…
BitBLT Graphics Hardware Accelerator (AXI Bus)
The DB9100AXI BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from comman…
The DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or…
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.
Stereo 3D depth value Correspondenc calculation with 64 disparities
iv-corr implements a 1-dimensional search algorithm for stereo correspondences in stereo pictures.
Real Time Image Rectification for HD pictures up to 1920x1080p60Hz
The IV-Rect IP implements picture rectification for high resolution images like HD (1280x720p60 or 1920x1080p30).
AMBA AXI from ARM Holdings is an high performance on-chip bus architecture.
The MVD ASI Transmitter core is a drop-in module that includes the following functions : • 188 or 204 bytes MPEG-TS input • 8B/10…
The UDP/IP core is a drop-in module which includes its own MAC to send and receive UDP packets on an Ethernet Network.
The MVD ATSC core is a drop-in module for FPGA that includes the following functions: - Input data framer from DVB-SPI source (MP…
10G TCP Offload Engine+MAC+PCIe+Host_IF Very-Low Latency (XTOE+PCIe)
INT 10012 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low Latency and Very High Perfor…