Stallable pipeline stage with width contraction
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
- Control Logic
- Multiple Uses
- Now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Stallable pipeline stage with width contraction
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with width expansion
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with protocol for multiway pipeline fork and join capability
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
LDO voltage regulator (output voltage 0 to 1.8 V)
Power supply voltage stabilizer converts supply voltage to voltage of the specified value and operates in two modes: DC/DC step d…
Programmable LDO voltage regulator (output voltage 1.6 to 2.2 V)
The regulator stabilizes the external voltage (supply voltage) and forms an output level of the specified value.
1.17 V Reference current and voltage source
Reference current and voltage source is used to supply any analog blocks.
RSA/ECC Public Key Accelerators with TRNG and AHB
The PKA-IP-150 is a family of Public Key Accelerators (PKA) IP cores designed for full scalability and an optimal “performance ov…
The AES-IP-38 (EIP-38) is IP for accelerating the AES symmetric cipher algorithm supporting GCM or XTS modes at extreme speeds up…
Small is beautiful...
NIST ESV certified, AIS-31, FIPS (SP800-90A/B/C) True Random Number Generator
The TRNG-IP-76 is a FIPS-compliant and certified IP core for True Random Number Generation (TRNG) with an optional post-processor…
RSA/ECC Public Key Accelerator Farm with TRNG and AHB
The EIP-154 PKI Farm engine, offers autonoumus processing of Public Key Operations.
Highly effective and small gate size Mosquito Noise Reducer
JVC KENWOOD's Mosquito Noise Reducer IP, which is already used in its products, is now available for licensing.
JPEG Codec 4K(YUV422) 96fps@200MHz,
The KJN-7EX conform to the JPEG baseline format/JPEG Extended DCT-based process for compressing/decompressing 8bit/12bit still im…
Display Controller – 4K Digital Cinema LCD Panels (AXI4/AXI Bus)
The DB9000AXI-DCI LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Inte…
PWM to Class D Amplifier Power Stage, SMIC 0.13um
The AR35S13A is a efficient H-BTL audio output driver IP for Class-D amplifier application.
Stereo PCM to PWM Converter, SMIC 0.18um
The AR35S18E is a digitally coded conversion IP that translates stereo 16-24bit pulse-code modulated (PCM) input data into pulse-…
The AR35S13B is a high-performance digital Class D Amplifier IP for mono speaker playback application.
Scalable and Programmable Co-processor
Simpulse’s Pulsar DSP IP Core is a scalable and programmable co-processor for the signal processing of complex embedded digital s…
Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support
The DQSPI is a revolutionary quad SPI designed to offer the fastest operations available for any serial SPI memory.
The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390.