TSMC CLN20SOC 20nm Clock Generator PLL - 350MHz-1750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 20nm
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TSMC CLN20SOC 20nm Clock Generator PLL - 350MHz-1750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
9.6 MHz to 25 MHz Low pass filter
Low pass filter (3rd order Chebyshev filter) is based on the gyrators with cut-off frequency adjustment in wide range.
130 to 930 MHz Low-noise amplifier
Low noise amplifier (LNA) is usually used as the first stage of receivers and is characterized by low noise figure and high linea…
5-bit programmable ECL high-frequency divider
The 5-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 that…
A efficient pipelined radix-2 squared FFT.
LVDS-based IOs The Bi-directional LVDS is in production from 90nm CMOS to 16/12nm FinFET and taped out in 7nm FinFET.
5 to 20 MHz Intermediate-frequency amplifier
IFA consists of 3-stages amplifier with tunable gain, AGC system, linear output buffer for differential analog output, analog-dig…
9-bit 2-channel 0.5 to 33 MSPS (8 to 500 kHz BW) delta-sigma ADC
The block is second order delta-sigma ADC with 5-level quantizer.
The AES MPEG-TS interface core allows to encrypt or decrypt MPEG-TS stream using the MVD AES encryption core.
8 to 512 kHz intermediate-frequency amplifier
The device is a t2-channel intermediate-frequency amplifier (IFA).
Stallable pipeline stage with width contraction
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with width expansion
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with protocol for multiway pipeline fork and join capability
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
LDO voltage regulator (output voltage 0 to 1.8 V)
Power supply voltage stabilizer converts supply voltage to voltage of the specified value and operates in two modes: DC/DC step d…
Programmable LDO voltage regulator (output voltage 1.6 to 2.2 V)
The regulator stabilizes the external voltage (supply voltage) and forms an output level of the specified value.
1.17 V Reference current and voltage source
Reference current and voltage source is used to supply any analog blocks.
RSA/ECC Public Key Accelerators with TRNG and AHB
The PKA-IP-150 is a family of Public Key Accelerators (PKA) IP cores designed for full scalability and an optimal “performance ov…
The AES-IP-38 (EIP-38) is IP for accelerating the AES symmetric cipher algorithm supporting GCM or XTS modes at extreme speeds up…
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