UMC L28HPM 28nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- UMC
- 28nm
- HPM
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UMC L28HPM 28nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
IEEE 802.1ae (MACsec) 100G Security Processor with Avalon-ST Interface
Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for e…
This design is a DVB-T2 OFDM demodulator, supplied as portable and synthesizable Verilog-2001 IP.
The logiCLK is a programmable clock generator logicBRICKS IP core with twelve independent and fully configurable clock outputs.
Lossless JPEG Codec Full HD(YUV422) 24fps@100MHz. (1Sample/clk)
KJN-1LSC conform to the Lossless JPEG format(ITU-T T.81 Annex H) and compress/decompress image data without data loss in comparis…
Interlaken is a royalty-free interconnect protocol that was developed by Cisco Systems and Cortina Systems in 2006.
0.8 to 25 MHz Intermediate-frequency amplifier
IFA consists of 4-stage amplifier with tunable gain, AGC system, linear output buffer for differential analog output, analog-digi…
4-bit programmable ECL LF divider (1…15 dividing ratio )
The 4-bit programmable ECL low-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 which…
9-bit programmable ECL HF divider
The 9-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 whic…
14-bit 8-channel 15 to 25 MSPS pipeline ADC
A block is a pipelined 8-channels ADC, built on a 12 1.5-bit multiplying DAC with sample data storage device and the final block …
AGDA21 is a 10bit 150MSPS current steering D/A converter.
AGDA11 is a 10bit current steering D/A converter.
High Throughput and Low Latency Compression Engine For SSD
The high performance compression IPhere compresses at the line rate of 16Gbps in ASIC or up to 64 Gbps for custom implementations.
AGAD12 is a 10bit 167MSPS Pipeline A/D converter.
TSMC 65GP 2Gb/s RX LVDS IO cell
IP
Library of LVDS IOs cells for TSMC 65GP
The nSIO2000_TS65GP_2V5_1V0 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.0V or…
Application Specific Instruction Set Processors (ASIPs) possess an instruction set which is tailored to benefit a specific applic…
SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
The DB-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfe…
The PowerVR Series7XE family is a range of ultra-efficient, -featured GPUs that includes the world’s smallest Android Extension P…
JPEG XS compression IP core for HD - Max fps: 60 - Color sampling: 4:2:2 / 4:0:0
intoPIX has developed various optimized TicoXS architectures running a different pixel per clock to target a wide range of resolu…