Vendor: nSilition Category: High-Speed

Library of LVDS IOs cells for TSMC 65GP

The nSIO2000_TS65GP_2V5_1V0 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.0V or…

TSMC 65nm GP Silicon Proven View all specifications

Overview

The nSIO2000_TS65GP_2V5_1V0 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.0V or 1.8V/1.0V, designed on the TSMC 65 GP technology. The library is composed according to the customer’s choice of cells.

Key features

  • TSMC 65 GP
  • 2.5V/1.0V IO/Core transistors
  • Fully compliant with TIA/EIA-644-A-2001
  • Multi-purpose reconfigurable IO
  • Point-to-point, point-to-multipoint or bus-based IC high-speed data communications
  • Intra-package (e.g. MCM or SIP) inter-die high-speed data communications
  • Backplane high-speed data communications
  • High-speed serial communications (HDMI, SATA, PCIeX, etc.)
  • Communication to LCD/OLED screens
  • Video sensor digital data interface

What’s Included?

  • GDS II layouts
  • LEF abstracts
  • CDL netlists
  • Liberty timings
  • Verilog description
  • A full datasheet
  • An integration note

Silicon Options

Foundry Node Process Maturity
TSMC 65nm GP Silicon Proven

Specifications

Identity

Part Number
nSIO2000_TS65GP 2V5_1V0_LIB
Vendor
nSilition
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Belgium

Frequently asked questions about High-Speed I/O Pad IP

What is Library of LVDS IOs cells for TSMC 65GP?

Library of LVDS IOs cells for TSMC 65GP is a High-Speed IP core from nSilition listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this High-Speed?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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