The K-best decoder is part of the MIMO decoder.
- Channel Coding
- Mature
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- WiFi IEEE 802.11n/ac, WiMAX…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The K-best decoder is part of the MIMO decoder.
The K-best decoder is part of the MIMO decoder.
Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 1…
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
In the downlink transmission, the physical downlink shared channel (PDSCH) carries the user data (Transport block).
In Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications.
TC5100 is a flexible LDPC encoder/decoder Core.
The ntAES_XTS IP Core is fully compliant with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations…
DPDK-aware FPGA/GPP data mover
Arkville provides a high-throughput line-rate agnostic conduit between FPGA hardware and GPP software.
The Arm® Cortex®-A55 is the most power efficient mid-range application CPU built on Arm DynamIQ technology.
ARM® Mali™-G72 is the second generation Bifrost-based GPU for High Performance products.
Configurable CAN Bus Controller IP with Flexible Data-Rate
The Controller Area Network (CAN) is widely used in automotive and industrial applications.
64-bit embedded processor, fully compliant with the RISC-V ISA
SiFive’s E51 Coreplex is a 64-bit embedded processor, fully compliant with the RISC-V ISA.
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC
The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption.
High Performance NVMe for PCIe-based storage
Typical storage controllers are composed of a communication interface and a Nandflash controller.
-40 to +125 º? Temperature & Voltage Sensor (Voltage measurement 2.0V - 3.0V)
T&V Sensor is a unique solution intended to continuously monitor IC status at several on-die locations.
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…