AES IP Core
Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 1…
Overview
Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 192 and 256).
The AES IP Core is fully verified against 'The advanced encryption standard algorithm validation suite (AESAVS)'.
The implementation of the AES IP Core exhibits very low latency, high speed, and low gate count with a simple interface for easy integration within SoC applications.
Key features
- High performance AES IP Core (Encryption and Decryption)
- Supports different key lengths of 128, 192, and 256 bits
- The core supports any input pattern with fixed length of 128 bits
- Pipelined core available
Applications
- Wi-Fi
- Long-term evolution (LTE)
- WiMAX (IEEE Std 802.16)
- Banking systems
- Secure Communications links
What’s Included?
- Synthesizable Verilog
- System Model (Matlab) and documentation
- Verilog Test Benches
- Documentation
Specifications
Identity
Security
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Symmetric Cryptography IP cores
What is AES IP Core?
AES IP Core is a Symmetric Crypto IP core from WASIELA listed on Semi IP Hub.
How should engineers evaluate this Symmetric Crypto?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.