The logiMEM DDR3 SDRAM Memory Controller is a size optimized, flexible, parametric and synthesizable Synchronous DRAM Controller …
- Controller
- DDR3
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The logiMEM DDR3 SDRAM Memory Controller is a size optimized, flexible, parametric and synthesizable Synchronous DRAM Controller …
D8530 bridge to APB, AHB, and AXI bus, it is a dual-channel USART (Universal Synchronous/Asynchronous Receiver/Transmitter) devic…
USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SAM 8LPP
The unified PHY complies with the USB, USB 3.0, Serial ATA, Peripheral Component Interconnect Express (PCIe), and USB 2.0 interfa…
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devic…
eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP
eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption.
Linear Low-Dropout Regulator (Output Voltage 0.6V)
1-VIA’s VSCOM4L400ALDO0V6 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulatio…
Linear Low-Dropout Regulator (Output Voltage 0.9V)
1-VIA’s VSCOM4L400ALDO0V9 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulatio…
Even the smallest, lowest-power audio devices embed AI capabilities to enhance the user experience.
10M/100M/1G/10G Managed/Unmanaged (TSN) Ethernet Switch IP Core
Multi-port, multi-rate managed Ethernet switch with Time-Sensitive Networking (TSN) capabilities
4.4 GHz To 7.75 GHz Low phase Noise Fractional-N Synthesizer
The WEA48S55T is a broadband fractional–N frequency synthesizer with integrated phase sync function.
MMWave 80GHz PLL with VCO frequency range 19.00-20.25 GHz
MMWave 80GHz Analog FracN PLL with VCO frequency range 19.00-20.25 GHz, Including Integrated PFD, CP, LPF, VCO
Bandgap Voltage Reference (0.6V and 0.8V References)
1-VIA’s VSCOM4l400ABG IP is a 1.8V low-noise unbuffered programmable 0.6 and 0.8V Bandgap Voltage References (BGR) with eight 50u…
MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus.
PCIe 6.0 Integrity and Data Encryption Security Module
PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to …
1.5G MIPI D-PHY in SMIC 130nm~28nm
The ACTT family of interface IP for MIPI protocols is the way with mobile-optimized low power and high performance.
256x8 Bits OTP (One-Time Programmable) IP, TSMC 40G 0.9/1.8V Process
The AT256X8T40G6AA is organized as 256 bits by 8 one-time programmable (OTP).
256x8 Bits OTP (One-Time Programmable) IP, TSMC 22ULP 0.8V/1.8V process
The AT256X8T22ULP6AA is organized as 256 bits by 8 one-time programmable (OTP).
4Kx32 Bits OTP (One-Time Programmable) IP, TSMC 40nm ULP 1.1V/2.5V Process
The AT4K32T40ULP7ZC is organized as 4K-bits by 32 one-time programmable (OTP).
1x64 Bits OTP (One-Time Programmable) IP, TSMC 0.18um Mixed-Signal 1.8V/3.3V Process
The AT1X64T180MM0AB is organized as one by 64 bits one-time programmable (OTP).
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)