CXL Controller IP Listing

PCI Express® (PCIe®) 6.0 links operating at 64 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions on…

• CXL

PCI Express® (PCIe®) 7.0 links operating at 128 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions o…

• Controller
• PCIe 7.0

The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.

• CXL
• Available
• CXL, PCI-SIG

The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…

• CXL
• In production
• Available
• CXL, PCI-SIG

The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…

• CXL
• In production
• Available
• CXL, PCI-SIG

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…

• CXL

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…

• PCIe / CXL IDE

SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most dem…

• Controller

Primesoc's CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.

• CXL
• Matured- FPGA validated
• Immediate
• CXL Spec V1.1

High-bandwidth, low-power and low-latency standardized die-to-die interconnect

• Controller + 1

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

The NVMe 2 Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP…

• Verification IP

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …

• TSMC
• 6nm
• N6

The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …

• TSMC
• 5nm
• N5A

The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …

• UCIe

The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …

• UCIe

The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …

• UCIe