LatticeMico32 Open, Free 32-Bit Soft Processor
The LatticeMico32™ is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensin…
Flash/ROM/SRAM Controller
PowerPC Bus Slave
DO-254 External Memory Controller 1.00a
Provides the control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through t…
AXI External Memory Controller
The AXI EMC ( Microcontroller Bus Architecture (AMBA®) extensible Interface (AXI) External memory controller) provides the contro…
XPS Multi-Channel External Memory Controller (SRAM/Flash)
The Xilinx Multi-Channel External Memory Controller (XPS MCH EMC) provides the control interface for external synchronous, asynch…
External Memory Interface (EMIF)
EMIF provides an smart way to verify the EMIF component of a SOC or a ASIC.
UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler.
UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Single Port SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.25um process
UMC 0.25um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process standard asynchronous high density Single Port Register File SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler.