How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Logicircuit, Inc.
Category:
DDR
DO-254 External Memory Controller 1.00a
Provides the control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through t…
Overview
Provides the control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface, designed to interface with the AXI4 interface.
Key features
- Supports AXI4 specification for AXI interface
- Full AXI4 slave interface supports 32-bit address bus and 32/64-bit data bus
- Supports 32-bit configurable AXI4-Lite control interface to access internal registers
- Supports Burst transfers of 1-256 beats for INCR burst type and 2, 4, 8, 16 beats for WRAP burst type
- Supports AXI narrow transfers, unaligned transfer type of transactions
- Supports multiple (up to 4) external memory banks
- Supports independent memory configuration of each memory bank
- Supports memory data widths of 64-bit, 32-bit, 16-bit and 8-bit for each of the memory banks
Benefits
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
What’s Included?
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.
Specifications
Identity
Part Number
10117
Vendor
Logicircuit, Inc.
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
DDR IP Hardening - Overview & Advance Tips
DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
Which DDR SDRAM Memory to Use and When
This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
DDR5/4/3/2: How Memory Density and Speed Increased with each Generation of DDR
Frequently asked questions about DDR Interface IP
What is DO-254 External Memory Controller 1.00a?
DO-254 External Memory Controller 1.00a is a DDR IP core from Logicircuit, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.