Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
1692 to 1973 MHz Voltage Controlled Oscillator
Voltage-controlled oscillator (VCO) is the generator that can be tuned over a wide range of frequencies by applying a control vol…
USB 2.0 PHY IP, Silicon Proven in UMC 28HPC
The USB 2.0 PHY IP Core offers a physical layer (PHY) solution for high performance and low power.
USB 2.0 PHY IP, Silicon Proven in UMC 40LP
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for excellent performance and low power consumption.
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 40LL
The combined PHY complies with the PIPE, Serial ATA, PCIe, USB, USB 3.0, USB 2.0, and PCIe Peripheral Component Interconnect Expr…
USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
The Combo PHY is a USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process.
USB 2.0 PHY IP, Silicon Proven in SMIC 40LL
The USB 2.0 PHY IP Core is a solution for the physical layer (PHY) that prioritizes both high performance and low power consumpti…
USB 2.0 PHY IP, Silicon Proven in SMIC 55LL
The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumpti…
USB 2.0 PHY IP, Silicon Proven in SMIC 14SF+
The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumpti…
USB 2.0 PHY IP, Silicon Proven in UMC 55SP/EF
The USB2.0 PHY IP is a physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 40LP/LL
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption.
1.013 to 1.217 GHz phase-locked loop
Frequency synthesizer built on PLL by dividing the integer coefficients.
1.68 to 1.917 GHz Phase-Locked Loop
Frequency synthesizer built on PLL by dividing the integer coefficients.
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 14SFP
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4…
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
The Peripheral Component Interconnect Express Gen3 PHY IP with PIPE 4.3 interface standard supported by this that complies with P…
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 40LP
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface sta…
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface sta…
50-800 MHz phase-locked loop frequency synthesizer
055TSMC_PLL_01 is an integer-N phase-locked loop frequency synthesizer (PLL), which produces stable clock signal in range from 50…