What is 50-800 MHz phase-locked loop frequency synthesizer?
50-800 MHz phase-locked loop frequency synthesizer is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Vendor:
NTLab
Category:
PLL
50-800 MHz phase-locked loop frequency synthesizer
055TSMC_PLL_01 is an integer-N phase-locked loop frequency synthesizer (PLL), which produces stable clock signal in range from 50…
Overview
055TSMC_PLL_01 is an integer-N phase-locked loop frequency synthesizer (PLL), which produces stable clock signal in range from 50 to 800 MHz. It works with reference frequency from 4 to 20 MHz. The block includes 400-800 MHz VCO, programmable N and R dividers, low noise digital phase-frequency detector (PFD), charge pump (CP) with integrated loop filter, frequency lock detector (FLD) and programmable output clock C divider.
Key features
- TSMC CMOS 55 nm
- Output frequency range from 50 MHz to 800 MHz
- Fully integrated VCO
- Reference frequency range from 4 MHz to 20 MHz
- Low current consumption
Block Diagram
055TSMC_PLL_01 block diagram
Applications
- Frequency clock generation
What’s Included?
- Schematic or NetList
- Abstract view (.lef and .lib files)
- Layout (optional)
- Behavioral model (for functional verification)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 55nm | GP | Silicon Proven |
Specifications
Identity
Part Number
055TSMC_PLL_01
Vendor
NTLab
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Lithuania
Frequently asked questions about PLL IP cores
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.