Vendor: T2M GmbH Category: Multi-Protocol PHY

PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC

This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface sta…

UMC 28nm HPC In Production View all specifications

Overview

This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface standard. Due to the support of an extra PLL control, reference clock control, and inbuilt power gating control, low power consumption is accomplished. Additionally, because the low power mode option is customizable, the PHY is extensively useful for a variety of settings with diverse power consumption considerations. PCIe PHY functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL.

Key features

  • Compliant with PCIe 3.0 Base Specification
  • Compliant with PIPE 4.3
  • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
  • Supported physical lane width: x4
  • Supported parallel interface: 32-bit
  • Supported input reference clock: 100 MHz
  • Supported parallel interface data clock: 62.5 MHz, 125 MHz, and 250 MHz
  • Supporting low power operation with configurable setting in power state P1/P2/L1 PM Substates:PLL control, reference clock control, and embedded power gating control
  • UMC 28nm HPC+ 1P7M5X1R (HVT/LVT/EHVT) process
  • Operating Voltage: 0.9V, 0.95V, 1.2V and 1.8V
  • Providing robust testability by low-cost Build-In Self-Test (BIST) via near-end analog and external loopback interface as well as far-end analog/digital loopback interface

Block Diagram

PCIe 3.0 Serdes PHY IP in 28HPC block diagram

What’s Included?

  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and
  • Standard Delay Format (SDF)
  • Synopsys library (LIB)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC In Production

Specifications

Identity

Part Number
PCIe 3.0 Serdes PHY IP in 28HPC
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Multi-Protocol PHY IP core

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Frequently asked questions about Multi-Protocol PHY IP cores

What is PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC?

PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC is a Multi-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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