JPEG Encoder Full HD(YUV422) 24fps@100MHz. (1Sample/clk)
The KJN-1ENC conform to the JPEG baseline format for compressing still images.
- Video Processing
- We also accept customization according to customer needs.
- ISO/IEC 10918-1, ITU-T T.81
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
JPEG Encoder Full HD(YUV422) 24fps@100MHz. (1Sample/clk)
The KJN-1ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec Full HD(YUV422) 24fps@100MHz.(1sample/clk)
The KJN-1+ conform to the JPEG baseline format for compressing/decompressing still images.
The LCD01G is a fully compatible GEO Mobile Radio (GMR-1) LDPC error control decoder.
Ultra-low-power 2.4 GHz transceiver for Bluetooth 5.3, 802.15.4 and IoT
icyTRX for the most demanding low-power applications The icyTRX ultra-low-power RF transceiver is designed to meet standards such…
Rail to rail LVDS receiver 1 Gbps
LVDS_RX is LVDS receiver with rail to rail input range.
The interface to the core logic includes signal pin (INP) to transmit data and control pin ( EN) to configure the state of the tr…
12-bit 2-channel 5 to 7.5 MSPS cascade delta-sigma ADC
The block is third order cascade (2-1) delta-sigma ADC with 5-level quantizer in both stages.
Four-Wire slave IP for use with the Mentor M8051W and M8051EW
The M4WIS adds four-wire slave capability to the M8051W and M8051EW microcontroller designs that are compatible with the I2C Fast…
Two-Wire slave IP for use with the Mentor M8051W and M8051EW
The M2WIS adds two-wire slave capability to M8051W and M8051EW designs.
Noesis Technologies ntOFDM_BBP is a custom baseband processor, which implements the physical layer of an OFDM, time division dupl…
The PowerVR Series7XT family pushes mobile and embedded GPU performance to new heights with configurations featuring 2 to 16 clus…
IP
LDO voltage regulator (output voltage 2.7 V)
The voltage regulator consists of differential amplifier which compares reference voltage with voltage from feedback divider.
2096 to 2916 MHz Voltage controlled oscillator
Voltage-controlled oscillator (VCO) is the generator that can be tuned over a wide range of frequencies by applying a control vol…
2693 to 3753 MHz Voltage controlled oscillator
Voltage-controlled oscillator (VCO) is the generator that can be tuned over a wide range of frequencies by applying a control vol…
Phased-locked loop 120 to 950 MHz
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multip…
Frequency synthesizer 20 to 300 MHz
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multip…
2D Graphics Hardware Accelerator (AXI4 Bus)
The DB9200AXI4 2D Graphics Hardware Accelerator / Engine Verilog IP Core renders graphics frames as follows: Generates bitmaps fr…
This design is a DVB-T2 OFDM demodulator, supplied as portable and synthesizable Verilog-2001 IP.
Lossless JPEG Codec Full HD(YUV422) 24fps@100MHz. (1Sample/clk)
KJN-1LSC conform to the Lossless JPEG format(ITU-T T.81 Annex H) and compress/decompress image data without data loss in comparis…