Interlaken is a royalty-free interconnect protocol that was developed by Cisco Systems and Cortina Systems in 2006.
- Interlaken
- Now
- Fully compliant with Interl…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Interlaken is a royalty-free interconnect protocol that was developed by Cisco Systems and Cortina Systems in 2006.
0.8 to 25 MHz Intermediate-frequency amplifier
IFA consists of 4-stage amplifier with tunable gain, AGC system, linear output buffer for differential analog output, analog-digi…
4-bit programmable ECL LF divider (1…15 dividing ratio )
The 4-bit programmable ECL low-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 which…
9-bit programmable ECL HF divider
The 9-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 whic…
14-bit 8-channel 15 to 25 MSPS pipeline ADC
A block is a pipelined 8-channels ADC, built on a 12 1.5-bit multiplying DAC with sample data storage device and the final block …
Application Specific Instruction Set Processors (ASIPs) possess an instruction set which is tailored to benefit a specific applic…
SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
The DB-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfe…
The PowerVR Series7XE family is a range of ultra-efficient, -featured GPUs that includes the world’s smallest Android Extension P…
The CCM1 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C.
IEEE 802.1ae (MACsec) Security Processor
Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for e…
IEEE 802.11 WAPI Encryption Core
Implementation of the new Chinese security standard (WAPI) requires running the SMS4 cipher in the WPI mode for encryption and me…
Ultra-Compact 3GPP Cipher Core
The ZUC1 core implements ZUC stream cipher in compliance with the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EI…
MicroBlaze™ is the Xilinx® 32-bit RISC Harvard architecture soft processor core with a rich instruction set optimized for embedde…
Shader architecture type 3D GPU
A shader architecture type 3D GPU Integrating the OpenVG 1.1 hardware processing pipeline
High-performance Processor for Real-time and Linux Applications
The Andes Technology N13 processor is a high performance CPU core architected for computation intensive applications running eith…
High-efficiency Low-power Processor
System-on-chip designs are proliferating to help OEMs automate functions such as smart lights, heating and cooling, wireless door…
Entry-level Low-Power 32-bit Processor
N705 is an ultra low-power small-size synthesizable general purpose 32-bit softcore embedded processor.
ISO 7816 Based Smart Card Reader
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications.
The DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO)…
I2C Controller IP – Master, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses
The DB-I2C-M-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon Bus to an I2C Bus …