HDMI eARC Receiver IIP

HDMI eARC RECEIVER interface provides full support for the two-wire HDMI eARC RECEIVER synchronous serial interface, compatible with HDMI specification.Through its HDMI eARC RECEIVER compatibility, it provides a simple interface to a wide range of low-cost devices. HDMI eARC RECEIVER IIP is proven in FPGA environment.The host interface of the HDMI eARC RECEIVER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

HDMI eARC Receiver IIP is supported natively in Verilog and VHDL

• Compliant with HDMI_eARC Receiver protocol standard of HDMI version 2.1 specification
• Full HDMI_eARC Receiver functionality
• Supports AXI4-Lite SOC interface
• Supports AXI4 stream for audio interface
• Supports legacy ARC IP
• Supports single-ended non-differential split outputs
• Supports the reception of the following encrypted or unencrypted audio formats.
• 2-channel L-PCM
• Multi-channel L-PCM
• IEC 61937
• One bit audio
• Supports ACP, ISRC1, and ISRC2 U-bit Messages Structures
• Supports ECC (Error Correcting Code) decoding and error correction.
• Supports biphase-mark decoding
• Supports falling-edge de-modulation.
• Supports the following functions over the eARC Common Mode Data Channel:
• Discovery and disconnect
• Heartbeat
• Status bits
• Audio Latency Control
• Capabilities Data Structure
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The HDMI eARC RECEIVER interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.