HDMI SOURCE IIP

The HDMI Source IIP core supports the HDMI 1.4b/2.0b/2.1 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. HDMI Source IIP is proven in FPGA environment. The host interface of the HDMI can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

HDMI SOURCE IIP is supported natively in Verilog and VHDL

• Compliant with HDMI specification 1.4b/2.0b/2.1.
• Full HDMI Source functionality.
• Compatible with DVI and Dual-Link DVI Standards.
• Supports 8, 10, 12 and 16 bit pixel inputs.
• Supports RGB, YCbCr444, YCbCr422 and YCbCr420 Colorimetric Formats.
• Supports 3D video formats and video resolutions of 4Kx2K, 5Kx2K, 8Kx4K, 10Kx4K.
• Compressed Video Transport VESA DSC 1.2a.
• Supports 340 Mcsc to 600 Mcsc TMDS Character Rate.
• Supports FRL Lane link rates of 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps.
• Supports Variable Refresh Rate (VRR) and Fast Vactive (FVA).
• Supports Info frames and auxiliary data formats in HDMI specification1.4b/2.0b/2.1
• Supports 2, 8 and 32 channel audio format.
• Supports 8b10b encoding on TMDS channel.
• Supports Fixed Rate Link transmission with 16b18b encoding.
• Supports Forward Error Correction (FEC).
• Supports High-bandwidth Digital Content Protection System (HDCP) 1.4/2.2/2.3.
• Supports display data channel (DDC).
• Supports Consumer Electronics Control (CEC1.4/2.0).
• Supports 10bit, 20bit, 40bit, and 80bit parallel interfaces
• Supports Audio Return Channel (ARC) and Enhanced Audio Return Channel (eARC) Receiver.
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The HDMI Source interface is available in Source and netlist products.
• The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.