The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction.
- Spacewire
- Compliant with ECSS-E-ST-50…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction.
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1-56Gbps Serdes - 7nm (Area-optimized)
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