Serial Front Panel Data Port Gen3
Serial Front Panel Data Port Gen3 is a next-generation, high bandwidth serial communications protocol defined by the ANSI/VITA 17…
Serial Front Panel Data Port (sFPDP) IP Core
The sFPDP core provides a IP solution for the VITA 17.1-2015 sFPDP specification.
Serial Front Panel Data Port is an industry standard, low-overhead, low-latency, high speed serial communications protocol.
Vital signs healthcare sensor interface
EN62020 can be interfaced with an array of ultra low-power biometric sensor front-ends for vital signs monitoring for healthcare …
Neuromorphic Processor IP (Second Generation)
Akida is a neural processor platform inspired by the cognitive ability and efficiency of the human brain.
Akida is a neural processor platform inspired by the cognitive ability and efficiency of the human brain.
These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either S…
Ultra-low-power 60 GHz radar-on-chip
Short-range radar has many potential applications, such as gesture control, contactless vital-signs monitoring, presence detectio…
Silicon agnostic, scalable implementation of IEEE-ISTO Std 4900-2021 The DiFi IP core is a scalable and silicon agnostic implemen…
GDDR5 Controller - Verifies memory compliance, boosts performance, and ensures reliability
The GDDR5 Memory Controller Verification IP (VIP) is a robust solution designed to verify the compliance and performance of GDDR5…
ML-KEM Key Encapsulation IP Core
The KiviPQC™-KEM is a hardware accelerator for post-quantum cryptographic operations.
The ICE-IP-63 (EIP-63) is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well …
Power Switch IPs are vital components in integrated circuits (ICs) designed to manage power distribution within electronic system…
Phase-Locked Loop (PLL) IPs are essential components in integrated circuits (ICs), providing precise frequency synthesis, clock g…
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devic…
Scalable Edge NPU IP for Generative AI
Ceva-NeuPro-M is a scalable NPU architecture, ideal for transformers, Vision Transformers (ViT), and generative AI applications, …
64-bit High performance Quad Core RISC-V Microprocessor
VEGA AS4161 features a quad core out-of-order processing engine with a 16-stage pipeline for high performance compute requirement…
64-bit High performance Dual Core Microprocessor
VEGA AS2161 features a dual core out-of-order processing engine with a 16-stage pipeline for high performance compute requirement…
64-bit High performance Single Core Microprocessor
VEGA AS1161 features an out-of-order processing engine with a 16 stage pipeline enabling it to meet next gen computational requir…
CPU-less QUIC Offload IP core for FPGA Acceleration
QUIC Client 10Gbps IP Core (QUIC10GC-IP) is engineered from the ground up to simplify the QUIC protocol with TLS 1.3 security int…