64-bit High performance Quad Core RISC-V Microprocessor
VEGA AS4161 features a quad core out-of-order processing engine with a 16-stage pipeline for high performance compute requirement…
64-bit RISC-V Single Core Microprocessor
VEGA AS1061 features an in-order processing engine with a 6 stage pipeline enabling it to meet high-performance embedded applicat…
InCore Azurite is an extremely compact, RISC-V 2-stage pipelined micro-processor.
InCore Calcite is a 32/64 Bit RISC-V in-order, single-issue 5-stage pipelined micro-processor.
The DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AX…
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus. I3C Basic Specification Design
The DB-I3C-BASIC-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI …
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus
The DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – …
SoC Security Platform / Hardware Root of Trust
GEON-SoC is an area-efficient, processor-agnostic, hardware root of trust for SoC designs.
I3C Controller IP- Slave, Parameterized FIFO, APB Bus
The DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
I3C Controller IP – Master, Parameterized FIFO, APB Bus
The DB-I3C-M-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
Display Controller – Ultra HD LCD / OLED Panels (AXI4/AXI Bus)
The DB9000AXI4-UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Int…
Display Controller – 4K Digital Cinema LCD Panels (AXI4/AXI Bus)
The DB9000AXI-DCI LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Inte…
Display Controller - LCD / OLED Panels (AXI4 Bus)
The DB9000AXI4 LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI4 Protoc…
Display Controller - LCD / OLED Panels (AXI Bus)
The DB9000AXI3 Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconn…
AMBA Bus Host to eSPI Controller/Target
eSPI Controller/Target RTL SystemVerilog IP Core
AMBA Bus Host to eSPI Controller
The Digital Blocks DB-eSPI-Controller-AMBA is a fully compliant Intel Enhanced Serial Peripheral Interface (eSPI) Base Specificat…
eSPI Target RTL SystemVerilog IP Core
The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using pr…
64-bit High performance Dual Core Microprocessor
VEGA AS2161 features a dual core out-of-order processing engine with a 16-stage pipeline for high performance compute requirement…
64-bit High performance Single Core Microprocessor
VEGA AS1161 features an out-of-order processing engine with a 16 stage pipeline enabling it to meet next gen computational requir…