Vendor: InCore Category: CPU

32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.

InCore Azurite is an extremely compact, RISC-V 2-stage pipelined micro-processor.

RISC-V View all specifications

Overview

InCore Azurite is an extremely compact, RISC-V 2-stage pipelined micro-processor. Built on Incore's proprietary deep-customization stack for microarchitectural exploration, Azurite delivers industry-beating performance in an exceptionally small silicon footprint. A 32-bit processor at the cost of a traditional 8-bit price point.

The Azurite core comes bundled as a compute subsystem, with integrated AMBA protocol interconnects (supports AXI4, AHB, APB) and uncore components (debug, trace, interrupt controllers etc).

Key features

  • 32-bit RISC-V core
  • 2-stage pipeline
  • Available in many versions:
    • RV32I[M][C][F][B][P][U]
  • 32/16 general purpose registers
  • Multiplier
    • Iterative (fixed latency or early-out)
    • Fast multiply (2-cycle)
  • RISC-V privilege mode support:
    • Machine
    • User
  • Optional FPU (single precision)
  • Optional tightly coupled memories (TCM)
  • Optional 8 or 16 PMP regions
  • Optional Internal interrupt controller
    • Up to 128 sources
  • Optional Standard RISC-V CLINT
  • Optional NMI
  • Optional Trace
  • RISC-V Debug module
  • 2/4 pin JTAG
  • 2-8 breakpoints/watchpoints

Block Diagram

Azurite block diagram

Benefits

  • Configurability
    • Over 2000 optimal design points
    • Custom RISC-V extensions supported
  • Time to Market
    • Compute subsystem (core, interconnect, uncore) to quick-start SoC development
  • PPA
    • Industry-beating performance and area

Applications

  • Consumer Electronics
  • IoT
  • Sensor Fusion
  • Motor Control
  • Industrial Controllers
  • Storage Controllers
  • Low-Power Embedded
  • Mixed Signal Embedded
  • Co-processors

What’s Included?

  • RTL (Verilog)
    • Fully synthesizable
    • Human-readable
  • Documentation:
    • Datasheet
    • User Guide
    • Integration Guide
    • Architecture Reference Guide
    • Programmer's Guide
  • Hardware Development Kit (HDK):
    • FPGA: Xilinx bitstream
    • Verification test suites
    • ASIC: Synthesis and Constraints scripts
  • Software Toolchain:
    • GCC Cross Compiler
    • GDB
    • Open OCD
    • Assembler
    • Disassembler
    • Linker
    • Instruction Set Simulator

Specifications

Identity

Part Number
Azurite
Vendor
InCore
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

InCore
HQ: India

Learn more about CPU IP core

InCore Unveils SoC Generator Platform: From Idea to FPGA Validation in Minutes; Demonstrates Silicon Proof of Auto-Generated SoC

At the heart of this innovation is InCore’s SoC Generator, a powerful automation platform built to radically simplify and accelerate SoC development. Traditionally, even FPGA-based prototyping of custom SoCs can take months due to the complex interplay of IP integration, interconnect design, and software readiness. InCore’s platform collapses this timeline to mere minutes – automatically generating interconnects, integrating IP, and producing all required collateral to boot software on FPGAs almost instantly.

Frequently asked questions about CPU IP cores

What is 32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.?

32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA. is a CPU IP core from InCore listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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