Certus Semiconductor has assembled several of the world’s foremost experts in IO and ESD design to offer our clients the ability to affordably tailor their IO libraries into the optimal fit for their products. Certus is offering the semiconductor industry a unique approach to custom IO libraries, including tailored IO designs, and ESD solutions based on simulations leveraging specialized silicon ESD models.
In addition to offering fast turnaround custom IO designs, Certus offers independent ESD design, review and debug services. Through partnerships, Certus is also able to provide ESD testing & TLP support.
Specialed 20V Analog I/O in TSMC 55nm
A TSMC 55nm LP Specialized 20V Analog I/O in Standard Low Voltage CMOS This silicon-proven TSMC 55nm LP 20V ESD cell is a high-vo…
Full Radiation-Hardened ESD Library in GF 12nm LP/LP+
Full Radiation-Hardened ESD Library in GF 12nm LP/LP+
Custom die-to-die interface in 12/16nm process technology.
RF ESD library in TSMC 55nm LP
RF ESD cells in TSMC 55nm LP targetting low-capacitance ESD protection.
6.5V ESD Clamp in 180nm Technology
Standalone 6.5V ESD Power Clamp in 180nm technology for use in wirebond or flipchip.
It supports standard I3C, high-speed I3C, and Ultra-higher-speed I3C modes.