Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

USB 2.0 PHY

The USB 2.0 PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.

Contact Provider Request Datasheet
PHY USB 2.0 View all specifications

Overview

The USB 2.0 PHY is a high-speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full/Low-Speed USB analog front-end with a built-in 8-bit/16-bit parallel interface. Optimized for portable applications, the PHY features low power dissipation in active and/or standby state, and a small area for low cost. The USB 2.0 PHY can be implemented as a discrete or integrated physical layer interface for any OTG device that complies with the On-The-Go and Embedded Host Supplement to the USB 2.0 Specification, or any host or peripheral that complies with the USB 2.0 Specification. It also supports battery charging function.

Key features

  • Compliant with the USB Specification
  • Compliant with the UTMI Specification Revision 1.05
  • Compliant with the UTMI+ Specification Revision 1.0 Level 3
  • Compliant with the On-The-Go (OTG) Specification Revision 2.0
  • Compliant with the Battery Charging Specification Revision 1.1
  • Supports 480 Mbit/s “High Speed”, 12 Mbit/s “Full Speed”, and 1.5 Mbit/s “Low Speed””
  • Supports 60 MHz/8-bit interface and 30 MHz/16-bit interface
  • Supports either crystal reference clock source or on-chip reference clock source
  • Supports multiple reference clock frequencies: 12 MHz, 19.2 MHz, 20 MHz, 24 MHz, 40 MHz, etc.
  • Integrates 45 Ω ± 10% termination, 1.5 kΩ pull-up and 15 kΩ pull-down resistor
  • Clock and data recovery from serial stream on the USB bus
  • Supports detection of USB reset, suspension, resume, and remote-wake-up features
  • Supports the test modes defined in the USB 2.0 Specification
  • Provides Built-in-Self-Test (BIST) mode

Block Diagram

Click to open fullscreen

Specifications

Identity

Part Number
USB2.0 PHY
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Controller / PHY
PHY

Standards & Interfaces

Supported Standards
USB 2.0

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact VeriSilicon Microelectronics (Shanghai) Co., Ltd.

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is USB 2.0 PHY?

USB 2.0 PHY is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP