Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

USB 3.2 PHY

The USB 3.2 SuperSpeed Plus PHY provides a range of USB 3.2 Gen2 host and peripheral applications at up to 10 Gbps per lane, whic…

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PHY USB 3.2 View all specifications

Overview

The USB 3.2 SuperSpeed Plus PHY provides a complete range of USB 3.2 Gen2 host and peripheral applications at up to 10 Gbps per lane, which can be flexibly configured with one lane or two lanes. The USB 3.2 PHY mode also integrates high-speed mixed signal circuits to support Gen1 (5 Gbps).

Key features

  • Fully compatible with:
    • USB 3.2 SuperSpeed Plus: Universal Serial Bus 3.2 Specification, Revision 1.1
  • Supports data rates:
    • USB 3.2 SuperSpeed Plus 10 Gbps (Gen 2) and 5 Gbps (Gen 1)
  • Supports all USB 3.2 power management modes
  • Spread spectrum clock (SSC) and data scrambling to minimize EMI
  • APB and I2C interfaces to access the internal registers for different applications
  • Multiple loopback and compliance test modes
  • Built-in BIST pattern generator and checker with programmable modes for stand-alone tests
  • On-chip Eye Opening Monitor (EOM) to measure the eye diagram at the RX side
  • Adaptive and configurable RX continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
  • Programmable TX feed-forward equalization (FFE)
  • 8b/10b and 128b/132b encoding and decoding implemented in hardware
  • Supports LFPS generation and detection
  • IEEE standards 1149.1 and 1149.6 (JTAG) boundary scan for internal visibility and control
  • Supports a wide range of reference clocks: 12/19.2/20/24/25/26/27/30/38.4/40/48/50/52/54/60/100/200 MHz

Block Diagram

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Specifications

Identity

Part Number
USB3.2 PHY
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Controller / PHY
PHY

Standards & Interfaces

Supported Standards
USB 3.2

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact VeriSilicon Microelectronics (Shanghai) Co., Ltd.

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Frequently asked questions about Single-Protocol PHY IP

What is USB 3.2 PHY?

USB 3.2 PHY is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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