USB 3.2 PHY

The USB 3.2 SuperSpeed Plus PHY provides a complete range of USB 3.2 Gen2 host and peripheral applications at up to 10 Gbps per lane, which can be flexibly configured with one lane or two lanes. The USB 3.2 PHY mode also integrates high-speed mixed signal circuits to support Gen1 (5 Gbps).

• Fully compatible with:
  • USB 3.2 SuperSpeed Plus: Universal Serial Bus 3.2 Specification, Revision 1.1
• Supports data rates:
  • USB 3.2 SuperSpeed Plus 10 Gbps (Gen 2) and 5 Gbps (Gen 1)
• Supports all USB 3.2 power management modes
• Spread spectrum clock (SSC) and data scrambling to minimize EMI
• APB and I2C interfaces to access the internal registers for different applications
• Multiple loopback and compliance test modes
• Built-in BIST pattern generator and checker with programmable modes for stand-alone tests
• On-chip Eye Opening Monitor (EOM) to measure the eye diagram at the RX side
• Adaptive and configurable RX continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
• Programmable TX feed-forward equalization (FFE)
• 8b/10b and 128b/132b encoding and decoding implemented in hardware
• Supports LFPS generation and detection
• IEEE standards 1149.1 and 1149.6 (JTAG) boundary scan for internal visibility and control
• Supports a wide range of reference clocks: 12/19.2/20/24/25/26/27/30/38.4/40/48/50/52/54/60/100/200 MHz