Vendor: ASICFPGA Category: ISP Image Signal Processor

Advanced 2D Noise Reduction core

ASICFPGA 2D Noise Reduction core: Noise reduction is a key issue in any camera system to improve the visual appearance of the ima…

Overview

ASICFPGA Advanced 2D Noise Reduction core: Noise reduction is a key issue in any camera system to improve the visual appearance of the images.
As the light level decreases, the noise level increases to get appropriate brightness levels in the camera system.
The performance of the new advanced 2D noise reduction core is much improved over the previous version core.
The new core removes much more color noise and luminance noise than the previous version core.
The new noise reduction core can keep edge sharpness in spite of removing noises.
The logic size and performance of the new core is adjusted by changing the parameter of RTL source code level.

Until a few years ago, camera ISPs used noise filtering algorithms to minimize logic size rather than improve performance.
Our previous noise reduction core also used these algorithms.
There are limits to the performance of noise filters using these algorithms.
To improve the noise reduction performance of cameras, including smartphone cameras,
many noise reduction algorithms including wavelet noise reduction have been developed.
With the development of these algorithms, noise reduction performance has been greatly improved these days.
Many studies have been conducted to improve the noise of still images mainly in non-real time.
However, real-time noise reduction is required for video noise reduction, and an algorithm of appropriate logic size is also required.
In the case of wavelet noise filtering, the noise removal performance is somewhat better than the previous algorithms,
but the logic size is significantly larger. Therefore, we have developed a new algorithm that performs better than wavelet noise filters and has a smaller logical size than wavelet noise filter. The new noise reduction filter core has significantly improved noise reduction performance compared to the previous version of the core, and can remove both color noise and luminance noise.
Nevertheless, sharpness is maintained. In previous versions of the core, the color noise reduction performance was insufficient when the noise level was large, causing problems with image quality. The new noise filter improves this problem.

Key features

  • 2D noise reduction filter
  • Advanced new noise reduction algorithm
  • Adjust the logic size and performance of core by changing the parameter of RTL source code level
  • Noise filtering in Bayer/YUV/RGB domain

What’s Included?

  • Original Verilog RTL source files
  • Functional simulation support
  • Full functionality in with no time outs

Specifications

Identity

Part Number
ASICFPGA Advanced 2D Noise Reduction core
Vendor
ASICFPGA
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Canada

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Frequently asked questions about ISP Image Signal Processor IP

What is Advanced 2D Noise Reduction core?

Advanced 2D Noise Reduction core is a ISP Image Signal Processor IP core from ASICFPGA listed on Semi IP Hub.

How should engineers evaluate this ISP Image Signal Processor?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ISP Image Signal Processor IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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