UDP/IP – 40 GbE Protocol Hardware Stack

The DB-UDP-IP-40GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 40 & 10 GbE network links. The DB-UDP-IP is a Verilog SoC IP Core targeting Intel/Altera and Xilinx FPGAs and ASIC/ASSP devices.

The image below depicts the UDP/IP Hardware Stack SoC IP Core embedded within an Altera / Xilinx FPGA device, connected on one side to a 40 GbE Ethernet MAC, and on the other side to the user application within the FPGA (i.e. either the FPGA logic fabric or embedded host processor).

• 40 GbE network links, including 10 GbE
• Low latency, high-performance wire-line performance
• Internet Protocol (IP) Packet Processor:
  • IP & ICMP (Internet Control Message Protocol) Protocol
  • Host IP address filter, IP header checksum check & generator, userselectable Maximum Transmission Unit (MTU), Unicast & MulticastPacket support
  • Compliance with IETF IPv4/IPv6 RFCs
• User Datagram Protocol (UDP) Packet Processor:
  • Support for up to 256 UDP Ports
  • UDP header checksum check & generator
  • Compliance with IETF UDP RFCs
• Address Resolution Protocol (ARP) Packet Processor (client/server) with 4-16 entry ARP cache
• VLAN Support, DHCP, IGMP, Jumb Frames
• Interface to Intel/Altera (Avalon-ST) & Xilinx & Synopsys 40G MAC
• High Speed Data Interface to user Host Application:
  • 128-bit / 256-bit AXI4-Stream
• Host set-up & control via Control & Status Registers and Interrupt Controller
  • 32-bit AXI4-Lite or APB or AHB
• Pipeline, High Clock Rate, Low Latency architecture & design
• Fully-synchronous, synthesizable RTL Verilog SoC IP core

• Verilog RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.