Overview
The IGMSLRX01A is a synchronous, ultra-high density one port register file compiler. It is developed with TSMC 7 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process. Different combinations of words, bits, and column-selected number (MUX) can be used to generate the most desirable configurations.
By requesting the desired size and timing constraints, the IGMSLRX01A compiler is capable of providing suitable synchronous RAM layout instances within minutes. It can automatically generate the data sheets, Verilog behavioral simulation models, place & route models, and test patterns for use in ASIC designs. The duty cycle length can be neglected as long as the setup/hold times and minimum high/low pulse widths are satisfied. This allows a more flexible clock falling edge during each operation. Both the word write and the bit write mask operations are supported.
Learn more about Register File IP core
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