Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
Single Port Register File compiler - TSMC 65 nm LP - Memory optimized for high density and high speed - compiler range up to 40 k
Overview
Key features
- Ultra high speed
- Up to 580 MHz in worst case for 512x32 cut
- Power reduction features
- Data retention mode at 1.2 V to divide leakage by a factor of 2.5 compared to simple stand by mode
- Data retention mode at 0.77 V to divide leakage by a factor of 7 compared to simple stand by mode
- Flexible power routing: connection to the power grid or from the periphery of the instance
- Optional Byte write (MUX 2 and 4) and bit-wise write capability (MUX 8)
- Smart periphery design to reach the highest density
- Up to 50% gain in density versus alternative memory depending on instance configuration
- Designed with the uHD HVt Pushed rule bit cell from foundry
- Easy integration
- MUX options
- Data range flexibility allows easy addition of bits for redundancy or ECC purposes
- Address range flexibility allows easy addition of single rows for redundancy purposes
- The Dolphin quality
- Complete mismatch validation of the memory architecture taking into account local and global dispersion
- Optional BIST for industrial fabrication test of instances
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Register File IP core
Thorough validation: the conundrum of Pulsed latch libraries turned practical as Spinner systems
A versatile Control Network of power domains in a low power SoC
Effective Optimization of Power Management Architectures through Four standard "Interfaces for the Distribution of Power"
Methodology to lower supply voltage of standard cell libraries
AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing
Frequently asked questions about Register File IP cores
What is Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k?
Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k is a Register File IP core from Dolphin Semiconductor listed on Semi IP Hub.
How should engineers evaluate this Register File?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Register File IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.