Why Hardware Monitoring Needs Infrastructure, Not Just Sensors
Discover why scaling modern SoCs requires more than just sensors. Learn how the proteanTecs hardware monitoring system uses a unified infrastructure to connect
Vendor:
iSTART-TEK Inc.
Category:
Monitoring
SRAM Test Solution
Easy to change SRAM testing algorithms after CP phases EZ-TEC can coexist with the existing memory testing circuits of chip desig…
Overview
Easy to change SRAM testing algorithms after CP phases
EZ-TEC can coexist with the existing memory testing circuits of chip design companies. This U. S. patent breaks down memory testing algorithms into elements, allowing users to reconstruct the architecture of any memory testing algorithm through element reorganization.
Interface
- SRAM Interface
- JTAG
- IEEE1500
- IEEE1149.1
- IEEE1687
- Basic
Key features
- Coexist with existing MBIST’s circuits
- Decouple existing SRAM testing algorithms from Elements
- Element-Based architecture testing algorithms for reducing area obviously
- Easy to change SRAM testing algorithms through JTAG interface, after finishing CP phases
Applications
- Allow users to change testing algorithms after CP stages
Specifications
Identity
Part Number
EZ-TEC
Vendor
iSTART-TEK Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Taiwan (R.O.C)
Learn more about Monitoring IP core
IMS: Intelligent Hardware Monitoring System for Secure SoCs
In the modern Systems-on-Chip (SoC), the Ad vanced eXtensible Interface (AXI) protocol exhibits security vulnerabilities, enabling partial or complete denial-of-service (DoS) through protocol-violation attacks. The recent counter- measures lack a dedicated real-time protocol semantic analysis and evade protocol compliance checks. This paper tackles this AXI vulnerability issue and presents an intelligent hardware monitoring system (IMS) for real-time detection of AXI protocol violations.
Same Chip, Two Destinies: How Power Profiles Improve With On-Chip Monitoring
What happens to critical power-related considerations when the same chip is handled two different ways, with or without visibility from within? This article begins by examining how the absence of on-chip monitoring impacts peak power, average power, and Di/Dt noise (rate of current change), as illustrated in the diagram below and the subsequent discussion. It then details how these aspects change when in-chip telemetry is available.
Runtime Energy Monitoring for RISC-V Soft-Cores
The authors propose a holistic approach to monitor energy consumption at runtime without the need of running complex (micro-)architectural models. Their approach is based on a measurement board coupled with a FPGA-based System-on-Module.
Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring
Unfortunately, precise thermal monitoring reached an inflection point at 2nm, with traditional solutions proving less practical below 3nm. To tackle the issue, this article delves into a novel approach, accurate to ±1.0°C, that overcomes this critical challenge.
Real-Time ESD Monitoring and Control in Semiconductor Manufacturing Environments With Silicon Chip of ESD Event Detection
Integrated circuits are susceptible to electrostatic discharge (ESD) events. Real-time detection and alerting of ESD events in semiconductor manufacturing environments is the key to achieving well ESD control. Additionally, the magnitude and duration of an ESD event are strongly correlated with the specific type of ESD events.
Frequently asked questions about system monitoring IP cores
What is SRAM Test Solution?
SRAM Test Solution is a Monitoring IP core from iSTART-TEK Inc. listed on Semi IP Hub.
How should engineers evaluate this Monitoring?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Monitoring IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.